Memory devices are typically provided as internal storage areas in a computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer, typically called a basic input output system (BIOS). Unlike RAM, ROM generally cannot be written to by a user. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased and programmed by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased in blocks instead of one byte at a time and reprogrammed. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bitline) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activating the other cells of the string for access, but allowing for a higher cell density). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. It is noted that other types of non-volatile memory exist which include, but not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), Magnetoresistive Random Access Memory (MRAM), Molecular Memory, Nitride Read Only Memory (NROM), and Carbon Nanotube Memory.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM's can be accessed quickly, but are volatile. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, 133 MHZ, 166 MHZ, or 200 MHZ, about three or four times faster than conventional FPM (Fast Page Mode) RAM, and about two to three times as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. An extended form of SDRAM that can transfer a data value on the rising and falling edge of the clock signal is called double data rate SDRAM (DDR SDRAM, or simply, DDR). Other forms of synchronous memory interfaces are also utilized in modern memories and memory systems, including, but not limited to, double data rate 2 SDRAM (DDR2), graphics double data rate (GDDR), graphics double data rate 2 (GDDR2), and Rambus DRAM (RDRAM).
Many computer systems are designed to operate using one or more forms of synchronous DRAM, but would benefit from non-volatile memory. A synchronous Flash memory has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, “Synchronous Flash Memory,” which is commonly assigned.
Read operations in many memory types typically include the steps of receiving a read command, receiving the requested address on the address lines of the memory device, decoding the requested memory address to select the desired page of memory cells from the array, waiting until the data from the selected page of memory cells is read from the bit lines that couple the data from the array to sense amplifiers, latching the page of read data from the sense amplifiers to an I/O buffer, and transferring the read data from the memory device. To speed up memory read operations, many memory types, in particular non-volatile memory types, include a cache read mode of operation. In a cache read operation, to reduce the overall latency of a read operation, the next page of data is read from the array by the sense amplifiers while the current page is being transferred from the device so that it will be ready to be latched into the I/O buffer once the current page of data is finished being transferred from the memory. The data read from the next page by the sense amplifiers is typically stored in a data cache latch. This allows the latency of the data sensing of the next page of data by the sense amplifiers and the data I/O of data words from the current page of data to run concurrently. In a cache read operation, the user only sees a full latency read operation for the initial page of data, while each following page of data is sensed concurrently with the I/O of the previous page.
The cache read operation, however, only allows for the current address to be incremented and the next sequential page of data to be sensed and read from the memory. If another page of data that is non-sequentially addressed is desired to read, the cache read operation must be terminated and a new read operation started with a new address. For each new non-sequential read operation the user must wait the full latency period of a standard/initial page read operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory, and in particular a non-volatile memory, with a reduced cache read mode latency.